2
RF Device Data
Freescale Semiconductor
MRF8S21140HR3 MRF8S21140HSR3
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22-A114)
2
(Minimum)
Machine Model (per EIA/JESD22-A115)
A
(Minimum)
Charge Device Model (per JESD22-C101)
IV
(Minimum)
Table 4. Electrical Characteristics (TA
= 25
°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Off Characteristics
Zero Gate Voltage Drain Leakage Current
(VDS
= 65 Vdc, V
GS
= 0 Vdc)
IDSS
—
—
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS
= 28 Vdc, V
GS
= 0 Vdc)
IDSS
—
—
1
μAdc
Gate-Source Leakage Current
(VGS
= 5 Vdc, V
DS
= 0 Vdc)
IGSS
—
—
1
μAdc
On Characteristics
Gate Threshold Voltage
(VDS
= 10 Vdc, I
D
= 200
μAdc)
VGS(th)
1.0
1.8
2.5
Vdc
Gate Quiescent Voltage
(VDS
= 28 Vdc, I
D
= 970
mAdc)
VGS(Q)
—
2.6
—
Vdc
Fixture Gate Quiescent Voltage (1)
(VDD
= 28 Vdc, I
D
= 970 mAdc, Measured in Functional Test)
VGG(Q)
3.8
5.2
6.8
Vdc
Drain-Source On-Voltage
(VGS
= 10 Vdc, I
D
= 3 Adc)
VDS(on)
0.1
0.18
0.3
Vdc
Functional Tests
(2)
(In Freescale Test Fixture, 50 ohm system) VDD
= 28 Vdc, I
DQ
= 970 mA, P
out
= 34 W Avg., f = 2140 MHz,
Single-Carrier W-CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ ±5 MHz Offset.
Power Gain
Gps
16.7
17.9
19.7
dB
Drain Efficiency
ηD
29.7
31.7
—
%
Output Peak-to-Average Ratio @ 0.01% Probability on CCDF
PAR
5.9
6.4
—
dB
Adjacent Channel Power Ratio
ACPR
—
-37.5
-36
dBc
Input Return Loss
IRL
—
-16
-7
dB
Typical Broadband Performance
(In Freescale Test Fixture, 50 ohm system) VDD
= 28 Vdc, I
DQ
= 970 mA, P
out
= 34 W Avg.,
Single-Carrier W-CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ ±5 MHz Offset.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
2110 MHz
17.7
32.1
6.2
-37.0
-17
2140 MHz
17.9
31.7
6.4
-37.5
-16
2170 MHz
18.1
31.7
6.4
-37.5
-16
V
GG
= 2 x V
GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit
schematic.
Part internally matched both on input and output.
(continued)
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